1. Field of the Invention
The present invention relates to logic circuits utilized in data processing systems. More particularly, the present invention includes an improved adder circuit used in various of the functional components contained in a computer system.
2. Description of Related Art
With the continual advance of computer technology, more and more circuitry is being provided on each integrated circuit (IC), which makes them correspondingly more complex. All aspects of the computer system, such as operating system and application software, system hardware, circuit design and the like are influenced by this ever increasing demand for higher performance. In the area of circuit design, new technologies have been developed to create more efficient integrated circuits in terms of speed and power consumption. One such technology is referred to as silicon-on-insulator (SOI). Basically, SOI refers to placing a thin layer of silicon on top of an insulator such as silicon oxide or glass. Transistors would then be built on top of this thin layer of SOI. The basic idea is that the SOI layer will reduce the capacitance of the switch, so it will operate faster. Due to the fact that the semiconductor sits on an insulator, the voltage drop across the transistor tends to vary. This situation is often referred to as the floating body effect and can have an effect on the switching times of SOI devices. Additionally, it has been discovered that N-channel type devices can experience scaling problems when implemented in SOI technology. This is due to the fact that N-type devices typically have a significant amount of electrical charge stored in the body of the device. As used herein, scaling refers to the ability to apply successive generations of process technology to the same circuit design. Based on the above, it can be seen that it would be advantageous to minimize the number of N-type devices that are present in SOI circuits. Further, it would be beneficial to balance any N-type devices with P-type devices such that the circuit configuration is symmetrical. That is, for sum circuits the N-type and corresponding P-type devices are on at the same time to minimize the floating body effect in SOI circuits, while for carry circuits the N-type and corresponding P-type devices would be on or off respectively to improve SOI performance.
In addition to scaling problems, the prior art often places too much dependence on gate voltage as a factor in increasing circuit speed. More specifically, in conventional circuits, such as Complementary Pass gate Logic (CPL), when a logic xe2x80x9c1xe2x80x9d is pushed through the source/drain of an N-channel type device, only a voltage of VDDxe2x88x92Vtn (VDD minus Vtn) is created at the other end (drain/source respectively), where Vtn is the threshold voltage of N-channel device. This Vtn voltage is restored through an inverter having a weak P-channel and strong N-channel type devices.
The speed of CPL circuit is very dependent on the xe2x80x9chighxe2x80x9d voltage that is applied to the gate of N-channel device to turn it on (conduct electricity) because of the following reasons: a) the higher the voltage applied to the gate, the harder (fast and distinct switching) the N-channel device is turned on and hence, the resistance is less and so is the RC component; b) the higher voltage applied at the gate, the higher the VDDxe2x88x92Vth voltage is with respect to the voltage appearing that the other end of the transistor (i.e. source or drain, respectively); and c) the higher the voltage VDDxe2x88x92Vtn, the easier it is to create a logic xe2x80x9c0xe2x80x9d at the output of the inverter because the |Vgs| of the N-channel device of the driving inverter is bigger.
The above described process means that the higher the xe2x80x9chighxe2x80x9d voltage in CPL circuits causes faster switching times. The converse is also true. That is, the lower the xe2x80x9chighxe2x80x9d voltage applied at the gate creates an avalanche effect, making the CPL circuit much slower. In the extreme case, if the VDDxe2x88x92Vtn voltage drops too much, it cannot even change the state of the inverter to create a logic xe2x80x9c0xe2x80x9d output.
On the chip, there are many sources that can cause the xe2x80x9chighxe2x80x9d voltage to be at a lower voltage level, such as couple noise, delta-I noise, and dc voltage drop. Further, with respect to SOI circuits, where the semiconductor sits on an insulator, the voltage drop across a transistor tends to vary. This situation is often referred to as the floating body effect (history effect) and can have a significant impact on the switching times of SOI devices.
The above description demonstrates the problems that can be encountered when modeling SOI circuits which in turn makes predicting circuit speeds difficult. As the result, the speed at which the device including the SOI circuits, such as a microprocessor, is expected to operate is difficult to determine with any certainty. As noted above, scaling means applying successive generations of process technology to the same circuit design. Unfortunately, for conventional SOI circuits, successive generations of process technology tends to mean that supply voltages (VDD) will be lower. Those skilled in the art will understand that supply voltages tend to become lower as process technology advances. Because of this fact, the speed of SOI circuits using complementary pass gate logic does not scale well when compared to other circuit families.
Thus, it would be beneficial to have circuits that are scaled well with successive generations of process technology wherein the circuit switching speed is not so dependent to gate voltage.
Adder circuits have been a major building block of computer systems for many years. In basic terms, adders are generally used to add two binary numbers and output the sum digit and a carry digit. Typically, the sum and carry digits are added to a subsequent stage and the process continues until all of the bits representing the numbers being added are summed. Several types of adders are widely known, including ripple carry adders, carry propagate adders and carry save adders (CSA). It is well known in the art that multipliers operate by performing multiple add and shift operations. Multipliers are often a component of an arithmetic logic unit (ALU) included in an execution unit of a microprocessor. For example, a fixed point, or integer unit in a microprocessor core that executes arithmetic instructions, such as multiply, add, divide, will include adders. Carry save adders are commonly used in high speed multipliers where they are generally able to function more rapidly than the other types of adders mentioned above. This is due to the fact that a CSA does not completely perform the relatively time consuming process of combining carries with sum bits between successive additions in the multiplication process, but instead defers this task until the final cycle of the multiplying operation. Typically, the partial products generated at each stage are then summed by carry save adders. The equations of sum and carry are outlined as follows:
sum=axe2x80x2bxe2x80x2c+abxe2x80x2cxe2x80x2+axe2x80x2bcxe2x80x2+abcxe2x80x83xe2x80x83(1)
carry=axe2x80x2bc+abxe2x80x2c+abcxe2x80x2+abcxe2x80x83xe2x80x83(2)
From these equations it can be seen that both true and complement signals are needed. Conventional techniques provide a circuit that generates a true signal and then merely adds an inverter to its output to generate the complement signal. Those skilled in the art will understand that the timing of these signals is such that the true signal will always be available before the complement signal. Thus, the true signal will have to be latched for a period of time while the complement signal develops. This not only causes increase time for the sum and carry to be generated, but also adds complexity to the design, since an accumulator, or the like must be included to store the signals while the complement develops. Further, conventional dual rail circuits, such as dual dynamic or dual rail regenerative cross-couple (RCPL) circuits have been used as adders. However, those skilled in the art will appreciate that the design of dynamic circuits requires special attention must be given to the macro interfaces and clocking due to the timing considerations. Further, RCPL circuits do not scale well with the new technologies, e.g SOI, particularly in the area of power distribution.
Therefore, it can be seen that it would be beneficial to have a static adder circuit that generated both the true and complement signals and made them available for processing the same time. That is, it would be advantageous to have a simultaneous dual rail (true and complement) circuit that generates the true and complement signals concurrently so they are available for processing in accordance with equations (1) and (2), above.
In contrast to the prior art, the present invention is a simultaneous dual rail, static, full adder circuit that balances the N-type and P-type devices to enhance the SOI technology.
Broadly, the present invention is an adder circuit that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that at the first two levels both the N-type devices and P-type devices are on at the same when that leg is to be open. The logic is then determined by a third level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. Thus, carryxe2x80x94 is generated by inputting the complement signals to a mirror of the same circuit used to generate the carry signal.
Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.